1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an auxiliary word line drive circuit for activating auxiliary word lines for memory cell selection according to a main word line controlled by a main decoder circuit and auxiliary word selecting lines controlled by an auxiliary decoder circuit.
2. Description of the Related Art
In recent years, semiconductor memory devices have been highly integrated for increased storage capacities at growing rates due to advances in the semiconductor microfabrication technology. Of the semiconductor memory devices, dynamic random-access memories (DRAM) capable of storing and holding data can easily be highly integrated for increased storage capacities because one memory cell comprises two components, i.e., a transistor and a capacitor. DRAMs having a storage capacity of gigabit have already been proposed in publications from related academic societies.
FIG. 1 of the accompanying drawings shows a DRAM memory cell. As shown in FIG. 1, the DRAM memory cell has a memory cell capacitor C1 which is kept at a power supply voltage Vcc through a memory cell transistor M1 or a ground potential GND. A threshold voltage Vtn of the memory cell transistor M1 is higher than threshold voltages of surrounding transistors for reducing a subthreshold leakage. For writing data into the memory cell capacitor C1, therefore, it is necessary to apply a voltage higher than the sum of the threshold voltage Vtn and the power supply voltage Vcc to a word line WL to which the memory cell transistor M1 is connected. As a result, an increased potential Vpp higher than the power supply voltage Vcc is applied through the word line WL to the gate of the memory cell transistor M1.
As the storage capacities of DRAMs increase, the power supply voltage supplied from an external source to the DRAMs decreases. For example, the power supply voltage for a DRAM having a storage capacity of 64,256 Mb is about 3.3 V, and the power supply voltage for a DRAM having a storage capacity of 1 Gb is about 2.5 V.
For high-speed operation of DRAMs with lowered power supply voltages, the threshold voltages of the memory cell transistors may be lowered to increase their driving capabilities. However, the lowered threshold voltages are responsible for poor subthreshold leakage characteristics.
The threshold voltages of memory cell transistors cannot be substantially lowered because of the need to reduce the subthreshold leakage, and cannot be scaled with respect to the power supply voltage. Accordingly, the increased voltage applied to the gate of the memory cell transistor cannot sufficiently be lowered, and it is difficult to obtain the increased voltage from the power supply voltage which is lowered.
For solving the above problems, it has been proposed to apply a negative voltage to a word line connected to a memory cell.
FIG. 2 of the accompanying drawings shows a first conventional semiconductor memory device (Japanese laid-open patent publication No. 84355/94) according to such a proposal, and FIG. 3 of the accompanying drawings shows a timing chart of operation of the first conventional semiconductor memory device.
In FIG. 2, word lines WL0, WL1 serve to carry signals to be applied to the gates of memory cell transistors M49.
In an unselected state, the gates of selecting transistors N66 in a word decoder 52 are kept at a ground potential GND, rendering the selecting transistors N66 nonconductive, and the gates of non-selecting transistors N68 are kept at a power supply potential Vcc, rendering the non-selecting transistors N68 conductive. Word line selecting signals 50a from a low-order address predecoder 53 have the ground potential GND. The word lines WL0, WL1 are kept at a negative potential VL which is of a low level, the negative potential VL being of a value smaller than the absolute value of a threshold voltage Vtn of the n-channel transistors N66.
In a selected state, in the word decoder 52, an address signal is applied at a time t1 to change the output signal from an NAND gate 60 to change from the Vcc potential to the negative potential VL. The gate potential of the transistors N66 changes to Vcc-Vtn, rendering the transistors N66 conductive, and the gate potential of the transistors N68 changes to the negative potential VL, rendering the transistors N68 nonconductive.
Therefore, all the word lines connected to the conducted transistors N66 are elevated from the negative potential VL to the ground potential GND.
In the low-order address predecoder 53, the potential of only a selected one of the word line selecting signals 50a changes to an increased potential VH in response to the applied address signal, thereby elevating a desired word line WL0 to the increased potential VH.
FIG. 4 shows a second conventional semiconductor memory device (Yamagata, T., et al., "Circuit Design Techniques for Low-Voltage Operating and/or Giga-Scale DRAMs", ISSCC Digest of Technical Papers, pp. 248-249, February, 1955).
In an unselected state, the output signal from a NAND gate 71 has a power supply potential Vcc. Therefore, the gate of a transistor N72 is kept at the power supply potential Vcc, rendering the transistor N72 conductive. An increased potential Vpp is applied to the gate of a transistor P72, which is rendered nonconductive. A word line WL is now kept at a negative potential Vbb.
When an address signal is applied to bring about a selected state, the output signal from the NAND gate 71 has a ground potential GND. The gate of the transistor N72 is kept at the negative potential Vbb, rendering the transistor N72 nonconductive. A ground potential GND is applied to the gate of the transistor P72, which is rendered conductive. The potential of the word line WL changes from the negative potential Vbb to the increased potential Vpp.
The above conventional semiconductor memory devices are disadvantageous for the following reasons:
According to the first conventional semiconductor memory device, the negative potential is set to an absolute value lower than the threshold voltage of the n-channel transistors, making it impossible to sufficiently lower the word line potential. Furthermore, when the word decoder 52 is activated, those word lines which are not selected by the word line selecting signals 50 change from the negative potential to the ground potential GND.
According to the second conventional semiconductor memory device, the negative potential or low level for the word line WL can be selected irrespective of the threshold voltage of the transistors. However, as the semiconductor memory device becomes smaller in size, it becomes difficult to line the word lines with metallized interconnections for reducing interconnection-induced delays at the pitch of the word lines. This drawback holds true for the first conventional semiconductor memory device, and presents obstacles to efforts to reduce the size and increase the storage capacity of semiconductor memory devices.